1. Field of the Invention
The present invention disclosed in the specification relates to a semiconductor device utilizing crystalline semiconductor, particularly to the constitution of an insulating gate type transistor. Further, the present invention relates to the constitution of a semiconductor circuit and an electrooptical device comprising such a transistor or the like and an electronic instrument compounded with these.
Further, in the specification, all of a transistor, a semiconductor circuit, an electrooptical device and an electronic instrument are dealt with by including them in the category of "semiconductor device". That is, all of devices capable of functioning by utilizing properties of a semiconductor are referred to as semiconductor devices. Accordingly, semiconductor devices described in the scope of claims include not only a single body of a transistor or the like but a semiconductor circuit and an electrooptical device integrated with these and an electronic instrument.
2. Description of Related Art
In the current state of VLSI (Very Large Scale Integrated Circuit) and ULSI (Ultra Large Scale Integrated Circuit), the element size tends to be more and more miniaturized in pursuit of promoting a further degree of integration. The trend is observed similarly in MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using a bulk single crystal and TFT (Thin Film Transistor) using a thin film. Currently, there has been requested an element having a channel length of 1 .mu.m or less, further, 0.2 .mu.m or less.
However, there has been known a phenomenon referred to as short channel effect as a factor for hampering miniaturization. The short channel effect gives rise to various problems of lowering of source/drain withstand voltage, lowering of threshold voltage and the like which are caused with a decrease in the channel length (refer to "Submicron Device I"; Mitsumasa Koyanagi et al., pp. 88-138, Maruzen Co., Ltd., 1987).
According to the reference, there has mostly known a punch through phenomenon as one of causes of the decrease in withstand voltage. According to the phenomenon, with a decrease in the channel length, potential influence of a depletion layer on the side of a drain effects on the side of a source and the diffusion potential on the side of the source is lowered (barrier lowering phenomenon induced by drain) by which there is brought about a situation in which control of majority carriers by the gate voltage becomes difficult.
Such a short channel effect poses a problem which must be overcome in carrying out miniaturization. Further, as a representative example of short channel effect, lowering of the threshold voltage is pointed out. This seems to be caused by widening of the depletion layer.
Although various countermeasures have been performed in respect of the short channel effect mentioned above, a countermeasure which is mostly carried out generally is channel dope. The channel dope is a technology for restraining the short channel effect by adding a very small amount of impurity elements such as P (phosphorus) or B (boron) over an entire channel forming region (Japanese Unexamined Patent Publication No. JP-A-4-206971, Japanese Unexamined Patent Publication No. JP-A-4-286339 and so on).
The channel dope is performed with a purpose of controlling the threshold voltage and restraining the punch through phenomenon. However, the channel dope technology is provided with a drawback of imposing serious restriction on the field effect mobility (hereinafter, referred to as mobility) of TFT. That is, movement of carriers is hampered by impurity elements which are added intentionally and the carrier mobility is significantly deteriorated.